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TK75005
ADVANCED INFORMATION FEATURES
s Can Be Used For Power Factor Correction/Line Harmonics Reduction to Meet IEC1000-3-2 Requirements s Maximum Duty Ratio 89% (typ.) s Low Standby Current for Current-Fed Start-Up s Current-Mode or Voltage-Mode Control s Internal User-Adjustable Slope Compensation s Pulse-by-Pulse Current Limiting
LOW-COST FLEXIBLE PWM CONTROLLER APPLICATIONS
s s s s Power Factor Correction Converters Off-Line Power Supplies Industrial Power Supplies Off-Line Battery Charger
TK75005
DRV
VCC EAOUT EAIN FB
DESCRIPTION
750 05
GND OVP
The TK75005 is an 8-pin PWM controller suitable for both voltage-mode and current-mode control. It also has advanced features not available in controllers with a higher pin count. One such feature is a sawtooth current flowing out of the feedback pin (FB), which provides a slope compensation ramp (in current mode applications) in proportion to the resistance terminating that FB pin. The TK75005 offers the same features as the TK75003 with the addition of the Error Amplifier and the Overvoltage Protection (OVP) functions, and the deletion of the Overcurrent Frequency Reduction feature. This PWM has features similar to the UC3842 (please refer to UC3842 Comparison Section).
SOP-8
CT
DRV
VCC EAOUT EAIN FB
7500
5
GND OVP
DIP-8
CT
BLOCK DIAGRAM
VCC ICT CT ICHG 175 A OSCILLATOR IDS 1.975 mA fCLK BANDGAP REFERENCE 10.0 V 8.0 V UVLO
ORDERING INFORMATION
TK75005
Tape/Reel Code Package Code Temp. Range
OVP 2.6 V CURRENT CONTROL DETECTOR GM STAGE 1.02 V SLOPE COMPENSATION PWM LATCH S Q DRV R OVERVOLTAGE DETECTOR
EAIN 2.5 V
PACKAGE CODE
D: DIP-8 M: SOP-8
TEMPERATURE RANGE
C: -40 TO 80 C
TAPE/REEL CODE
TL: Tape Left MG: Magazine
FB
EAOUT
GND
January 1999 TOKO, Inc.
Page 1
TK75005
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Low Impedance) ............................ 18 V Supply Voltage (ICC < 30 mA) ...................... Self Limiting Power Dissipation (Note 1) ................................ 800 mW Output Energy ........................................................... 5 J CT and FB Pins ........................................................ 10 V Junction Temperature ........................................... 150 C Storage Temperature Range ................... -55 to +150 C Operating Temperature Range ...................-20 to +80 C Extended Temperature Range ................... -40 to +85 C Lead Soldering Temperature (10 s) ...................... 235 C
TK75005 ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 13 V, CCC = 4.7 F, CT = 680 pF, CDRV = 1000 pF, TA = Tj = Full Operating Temperature Range, unless otherwise specified.
SYMBOL ICC(START) ICC(ON) VCC(ON) VCC(OFF) VHYST PARAMETER Start-up Supply Current Operating Supply Current UVLO Voltage ON UVLO Voltage OFF UVLO Hysteresis TEST CONDITIONS Current Source to VIN Pin EAIN = 2 V EAIN = 3 V VCC Sweeps Upward VCC Sweeps Downward 9 7 1 MIN TYP 0.25 12 14.5 10 8 2.0 MAX 0.9 17 19.0 11 9 UNITS mA mA mA V V V
OSCILLATOR SECTION (CT PIN) fDRV VCT(PK) VCT(VL) ICT(DIS) CT(MAX) Frequency at DRV Pin (Note 3) Peak Voltage Valley Voltage Discharge Current Maximum Timing Capacitance VCT = VCT(PK) 1.0 4.7 TA = Tj = 25 C TA = Tj = Full Range 90 85 2.5 3.2 1.1 1.8 3.0 100 110 115 3.9 kHz kHz V V mA nF
CURRENT DETECTOR, OVERVOLTAGE PROTECTION (OVP PIN) AND SLOPE COMPENSATION SECTIONS VCCD tCCD VOVD tOVP iSC(PK) iSC(VL) iSC(PK-VL) Current Control Detector Reference Voltage Propogation Delay to DRV Pin Overvoltage Protection Detector Reference Voltage Propogation Delay to DRV Pin Slope Compensation Peak Current Slope Compensation Valley Current Slope Compensation Peak to Valley TA = Tj = 25 C TA = Tj = Full Range VFB steps from 0 to 2 V TA = Tj = 25 C TA = Tj = Full Range VOVP steps from 2 to 3 V CT Pin = VCT(PK), TA = Tj = 25 C, EAOUT(HIGH) ,(Note 2) CT Pin = VCT(VL), TA = Tj = 25 C, EAOUT(HIGH) ,(Note 2) CT Pin = VCT(PK), TA = Tj = 25 C, EAOUT(HIGH) ,(Note 2) -250 -55 -215 2.51 2.46 80 -205 -30 -175 0.99 0.966 80 2.60 1.02 1.05 1.077 180 2.69 2.74 180 -160 -5 -135 V V ns V V ns A A A
Page 2
January 1999 TOKO, Inc.
TK75005
TK75005 ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: VCC = 13 V, CCC = 4.7 F, CT = 680 pF, CDRV = 1000 pF, TA = Tj = Full Operating Temperature Range, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIER AND GM STAGE SECTIONS (EAIN AND EAOUT PINS) Vref IIB AVD Reference Voltage Input Bias Current Open Loop Gain Unity Gain Bandwidth PSRR IOUT(SINK) IOUT(SOURCE) VOUT(HIGH) VOUT(LOW) IGM(MAX) IGM(MIN) Power Supply Rejection Ratio Output Sink Current Output Source Current VOUT(HIGH) at EAOUT Pin VOUT(LOW) at EAOUT Pin IOUT(MAX) at FB Pin from GM Stage IOUT(MIN) at FB Pin from GM Stage (Note 3) (Note 3) EAOUT = 1.2 V EAOUT = 3.5 V EAIN @ 2 V EAIN @ 3 V EAOUT(LOW), FB @ 2 V EAOUT(HIGH), FB @ 2 V -1.95 3.5 60 2 65 T A = T j = 25 C TA = Tj = Full Range 2.43 2.37 1.0 75 2 70 6.8 -1.1 4.1 0.4 -1.50 -1.0 0.7 -1.05 -0.5 2.50 2.57 2.64 V V A dB MHz dB mA mA V V mA A
OUTPUT SECTION (DRV PIN) DDRV(MAX) tDRV(RISE) tDRV(FALL) VDRV(HIGH) Maximim Duty ratio Rise Time Fall Time Output Voltage HIGH 1000 pF load 1000 pF load IDRV = -40 mA IDRV = 100 mA IDRV = -40 mA VDRV(LOW) Output Voltage LOW IDRV = 100 mA IDRV = 5 mA, VIN = 6 V 10.1 10.0 86 89 25 25 11.0 10.8 0.1 0.2 0.9 0.25 0.50 1.50 92 75 75 % ns ns V V V V V
Note 1: Power dissipation for both packages (TK75005M and TK75005D) is 800 mW when mounted. Derate at 6.4 mW/C for operation above 25 C. Note 2: For temperature dependence refer to "Slope Compensation Peak Current vs. Temperature" graph. Note 3: Guaranteed by design; not 100% tested.
January 1999 TOKO, Inc.
Page 3
TK75005
TEST CIRCUIT
DRV 1 nF GND 100 k OVP CT CT 680pF 3k 3k INV AMP IN EAIN FB EAOUT
VCC CCC 4.7 F
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT vs. SUPPLY VOLTAGE 20 16 DEVICE ON
FREQUENCY AT DRV PIN VS. TIMING CAPACITANCE (-25 TO 85 C) 10000
SLOPE COMPENSATION PEAK CURRENT vs. TEMPERATURE -100
FREQUENCY (kHz)
-140 ISC(PK) (A)
1000
ICC (mA)
12 0.8 0.4 0.0
-180
STANDBY
100
-220
0
4
8
12
16
20
10 10
100
1000 CT (pF)
10000
-260 -50
0
50
100
VCC (V) SUPPLY CURRENT vs. FREQUENCY AT DRV 50 40 CDRV = 1 nF
TEMPERATURE (C)
REFERENCE VOLTAGE vs. TEMPERATURE 2.6
600
SLOPE COMPENSATION RAMP
ISC(PK)
2.56
450
ICC (mA)
30 20 10 0 CDRV = 470 pF
Vref (V)
2.52 2.48 2.44
VFB (mV)
ISC(PK) - ISC(VL)
300 150
ISC(VL)
CDRV = 0 pF 0 400 800 1200 1600
0
RFB = 3 k TO GND CT = 680 pF, EAOUT(HIGH)
2.40 -50
0
50
100
0
5
10 TIME (s)
15
20
FREQUENCY (kHz)
TEMPERATURE (C)
Page 4
January 1999 TOKO, Inc.
TK75005
PIN DESCRIPTIONS
DRIVE PIN (DRV) This pin drives the external MOSFET with a totem pole output stage capable of sinking or sourcing a peak current of about 1 A. In standby mode, the DRV pin can sink about 5 mA while keeping the drive pin pulled down to about 1 V. This ensures that the external MOSFET can not be inadvertently turned on by leakage currents. The maximum duty cycle of the output signal is typically 89%. GROUND PIN (GND) This pin provides ground return for the IC. OVERVOLTAGE PROTECTION INPUT PIN (OVP) This pin provides a means of turning off the external transistor drive output independent of the PWM loop. This pin is normally used for overvoltage protection, but can also be used to provide a drive disabled function. The pin is the input to comparator with its other input referenced to 2.6 V, which tracks Vref of error amp over temperature. and its output controlling the output driver of the IC. Therefore, if a voltage appears at this pin over 2.6 V, the voltage at the DRV pin drops to zero. TIMING CAPACITOR PIN (CT) The external timing capacitor is connected to the CT pin. That capacitor is the only component needed for setting the clock frequency. The frequency measured at the CT pin is the same frequency as measured at the DRV pin. As the frequency of operation increases above 200 kHz, the maximum duty cycle decreases from a typical 89% at 200 kHz to 82% at 1.6 MHz. The maximum recommended clock frequency of the device is 1.6 MHz. At normal operation, during the rising section of the timing-capacitor voltage, a trimmed internal current of 175 A flows out from the C pin and charges the capacitor. During the falling T section of the timing-capacitor voltage, an internal current of about 1.8 mA discharges the capacitor. FEEDBACK INPUT PIN (FB) The feedback pin normally receives the sum of three signals: the switch current signal, the error signal (from the internal error amplifier and the GM stage), and a voltage ramp (from an internal sawtooth-shaped current with a peak value of about 205 A) generated across the external terminating resistance. The switch current signal is needed January 1999 TOKO, Inc. in current-mode controlled converters and in converters with cycle-by-cycle overload protection. The error signal is needed for stabilizing the output voltage or current. The voltage ramp is needed for slope compensation (necessary for avoiding subharmonic instability in constant-frequency peak-current controlled current-mode converters above 50% duty ratio), or for Pulse Width Modulation (PWM) (in voltage-mode controlled converters). At higher clock frequencies, the bandwidth limitation of the internally-generated sawtooth-shaped current source becomes more apparent. The degree to which ramp bandwidth is tolerable depends on performance requirements at narrow pulse widths. A low impedance at the feedback pin can effectively eliminate the internallygenerated ramp effects and an external ramp can be readily created to attain higher performance at high frequencies, if desired. ERROR AMPLIFIER COMPENSATION INPUT PIN (EAIN) This pin is the inverting input of an operational amplifier which has its non-inverting input connected to 2.5 V. This is called the error amp because it amplifies the error between this pin's voltage and 2.5 V reference, which should reflect the error in the power supply's output regulation. The error amp provides a high gain stage so that the voltage loop gain can be high enough to provide good output voltage regulation.
ERROR AMPLIFIER COMPENSATION OUTPUT PIN (EAOUT)
This pin is the output of the operational amplifier mentioned in the EAIN pin description. By picking the proper resistor and capacitor network connected between pins 6 and 7, the gain and frequency response of the error amp block of the voltage loop can be set, thus providing gain and frequency compensation into the PWM voltage loop as needed. This pin also acts as the input to the GM stage of the voltage control loop. SUPPLY VOLTAGE PIN (VCC) This pin is connected to the supply voltage. The IC is in a low-current (250 A typ.) standby mode before the supply voltage exceeds 10 V (typ.), which is the upper threshold of the undervoltage lockout circuit. The IC switches back to standby mode when the supply voltage drops below 8 V (typ.).
Page 5
TK75005
THEORY OF OPERATION
The TK75005 is intended for use as a highly flexible primary-side PWM controller. The TK75005 is much like the TK75003 with the addition of an error amplifier, a GM stage and an overvoltage comparator, and the deletion of the TK75003 overcurrent frequency reduction feature. The many features integrated into a simple 8-pin design allow it to be easily configured for voltage-mode or currentmode control, fixed frequency or fixed off-time operation, off-line boot-strapping, and direct drive of a power MOSFET. Using a control technique referenced in the "Application Information" section, the TK75005 can be used as a highly cost-effective controller for power factor correction. The most noteworthy integrated feature in the TK75005 is the way in which the feedback control pin is configured to receive the error signal and the current signal for currentmode control. Rather than receiving both inputs into a comparator, a single input receives both signals summed together and compares them against a fixed internal reference. This yields two desirable effects: 1) a currentlimit threshold is automatically established, and 2) the required error-signal polarity is the inverse of that of a standard two-input current-mode control system. Generally, the signal summation requires no additional external components and adds the flexibility to add more control signals if desired. Another function is integrated into the FB pin. A current ramp, which can be used to establish either the slopecompensation ramp for a current-mode control design or the voltage-comparison ramp for a voltage-mode control design, flows out of the FB pin. By adjusting the terminating resistance at the FB pin, the desired ramp magnitude is established. The switching frequency is determined by an internal current source charging an external timing capacitor. The timing capacitor is ramped between internally-fixed thresholds, valley to peak, and then quickly discharged. A fixed off-time control technique can readily be implemented by using a small transistor to keep the timing capacitor discharged during the on-time. When the on-pulse is terminated, the timing capacitor ramps up to a fixed threshold at a fixed rate to set the off-time. The Undervoltage Lockout (UVLO) feature with hysteresis minimizes the start-up current which allows a low-power boot-strap technique to be used for the housekeeping power. The duty ratio of the TK75005 is limited to approximately 89% by the time required to discharge the Page 6 January 1999 TOKO, Inc. timing ramp. UC3842 COMPARISON Similarities to the UC3842 1) a single-ended transistor driver output with similar drive performance 2) an inverting error amplifier referenced to 2.5 V with similar electrical characteristics 3) a maximum threshold of ~1V on the current sense voltage used to terminate the PWM pulse 4) an 8-pin SOP-8 or DIP-8 package Unique features of the TK75005 1) a multi-signal summation point at the FB pin, instead of a single function UC1842 C/S pin 2) built-in slope compensation sawtooth current coming out of the FB pin, reduced parts 3) an overvoltage protection pin compared to 2.6 V 4) switching frequency set using a single capacitor, reduced parts 5) different UVLO thresholds 10 V / 8 V 6) maximum duty cycle set at 89%
TK75005
APPLICATIONS INFORMATION
BOOST POWER FACTOR CORRECTOR APPLICATION CIRCUIT Figure 7 shows a universal-input, 100 W boost power factor corrector application circuit. The control technique is called "current-clamped control." Both the control technique and the application circuit with waveforms are described in the paper "Low-Cost Power Factor Correction/LineHarmonics Reduction with Current-Clamped Boost Converter," published in the conference proceedings of Power Conversion Electronics '95/Powersystems WorldTM '95. A copy of the paper can be obtained by contacting Toko. For designers who wish to explore other performance optimizations of the current-clamped boost power factor corrector, aside from the conference paper Toko offers a Mathcad(c) file which can accurately display current waveforms and predict power factor, harmonic distortion, and individual harmonic currents. The Mathcad file and the text which describes how to use it are available from the Colorado Springs Toko IC Design Center. The power factor corrector in Figure 7 has been optimized for general wide-range-input use. In order to obtain the same performance at power levels other than 100 W, the control components do not need to change. The power component values change as follows: C8 scales in proportion to the power level, and L1 and R8 scales in inverse proportion to the power level. Typically, although not directly related to the line-current shaping capability of the application circuit, C1 and C10 would scale in proportion to the power level. All the components in the power stage should have a current rating as needed to accommodate the power level. Below is a step-by-step design example, showing how to determine the resistance of R7 terminating the feedback pin and the resistance of the current-sense resistor R8, for the boost corrector of Figure 7. Assumptions: Output power: Output voltage: Minimum line voltage: Efficiency at 85 Vrms: January 1999 TOKO, Inc. POUT = 100 W VOUT = 380 Vdc VI(MIN) = 85 Vrms EFF = 0.93 Page 7 R7 = DMAX x VCCD / ISC(PK) = 4.312 kohms Switching frequency: Inductance of boost inductor: f = 100 kHz L1 = 2.5 mH
Maximum duty ratio of TK75005: DMAX = 0.88 Peak value of ramp current flowing out of the FB pin: Threshold voltage of the current-control detector: Calculations: Peak value of minimum line voltage: VI(MIN)(PK) = ISC(PK) = 200 A VCCD = 0.98 V
2 x VI(MIN) = 120 VPK
Switch duty ratio at peak of minimum line voltage:
D = 1 - VI(MIN)(PK) / VOUT = 0.684 Peak-to-peak ripple current in inductor L1: I = VI(MIN)(PK) x D / (f x L1) = 0.33 A Input power at minimum line voltage:
PI = POUT / EFF = 107.5 W
Peak current in L1 (at peak of minimum line voltage):
IL1(PK) =
2 x PI / VI(MIN)(PK) + I/2 = 1.95 A
Resistance of resistor R7 (Note 1):
TK75005
APPLICATIONS INFORMATION (CONT.)
Select for R7: R7 = 4.3 kohms Resistance of current-sense resistor R8 (Note 2): R8 = (VCCD - ISC(PK) x R7 x D) / IL1(PK) = 0.201 ohms Select for R8: R8 = 0.18 ohms
Note 1: This value of R7 ensures that the line current will be zero around the zero-crossing of the line voltage, which is the required condition for low-distortion line current. Note 2: This value of R8 ensures that the sum of the voltage drop across R8 (caused by the peak inductor current) and the voltage drop across R 7 (caused by the instantaneous value of the stabilizing current) is equal to the threshold voltage of the current-control detector at the peak of the line voltage.
F1 250 V/ 2 A
TH1 10 B1 4 600 V, 1.5 A 2.5 mH t: 220 ETD-29 core gap in center leg
85-265 VAC
C1 0.1 F
2
1 R1a 24 k 0.5 W R1b 24 k 0.5 W D1 1N4148
L1
D3 HFA04TB60
3
t:9 C3 100 nF C7 C4 100 nF
R11a 200 k 0.25 W R11b 200 k 0.25 W R10 3k
R51a 200 k 0.25 W
380 V DC 100 W R51b 200 k 0.25 W
R2 5.6 k D4 30 V C10 1 nF 400 V C2 470 F D2 IN4148
1F R9 100 k EAOUT EAIN VCC OVP FB DRV CT
C8 100 F 400 V
R4 150 k
R5 10 R6 51
Q1 IRF840 R52 2.43 k R8 0.18 0.5 W
GND U1 TK75005
R3 5.6 k
C5 680 pF
C6 10 nF
R12 2.43 k
R7 4.3 k
FIGURE 7: BOOST POWER FACTOR CORRECTOR APPLICATION CIRCUIT Page 8 January 1999 TOKO, Inc.
TK75005
PACKAGE OUTLINE
8 5
DIP-8
6.4
Marking Lot Number
Marking Information
Marking xxx
Country of Origin
TK75005
1
4
9.5
3.3
0.5 min
3.3
+ 0.3
3.8
+ 0.3
0.25
e + 0.15 - 0.05
+ 0.15 - 0.05
e1
7.62
0~
15
2.54
0.46
0.25
M
Dimensions are shown in millimeters Tolerance: x.x = 0.2 mm (unless otherwise specified)
0.76
SOP-8
8 5
1.27
3.9
e 1.27
Recommended Mount Pad
1
4
e1
0.5 4.89
+ 0.3
5.4 0 ~ 10 0.2
6.07
+ 0.3
1.45
0.42
1.27 0.1
0.12
l
Dimensions are shown in millimeters Tolerance: x.x = 0.2 mm (unless otherwise specified)
0 ~ 0.25
e
1.64
Toko America, Inc. Headquarters 1250 Feehanville Drive, Mount Prospect, Illinois 60056 Tel: (847) 297-0070 Fax: (847) 699-7864
TOKO AMERICA REGIONAL OFFICES
Midwest Regional Office Toko America, Inc. 1250 Feehanville Drive Mount Prospect, IL 60056 Tel: (847) 297-0070 Fax: (847) 699-7864 Western Regional Office Toko America, Inc. 2480 North First Street , Suite 260 San Jose, CA 95131 Tel: (408) 432-8281 Fax: (408) 943-9790 Eastern Regional Office Toko America, Inc. 107 Mill Plain Road Danbury, CT 06811 Tel: (203) 748-6871 Fax: (203) 797-1223 Semiconductor Technical Support Toko Design Center 4755 Forge Road Colorado Springs, CO 80907 Tel: (719) 528-2200 Fax: (719) 528-2375
Visit our Internet site at http://www.tokoam.com
The information furnished by TOKO, Inc. is believed to be accurate and reliable. However, TOKO reserves the right to make changes or improvements in the design, specification or manufacture of its products without further notice. TOKO does not assume any liability arising from the application or use of any product or circuit described herein, nor for any infringements of patents or other rights of third parties which may result from the use of its products. No license is granted by implication or otherwise under any patent or patent rights of TOKO, Inc.
January 1999 TOKO, Inc.
(c) 1999 Toko, Inc. All Rights Reserved IC-xxx-TK75005 0798O0.0K
Page 9
Printed in the USA

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